In recent years, in the field of non-volatile semiconductor memories such as NAND cell type flash memories (hereinafter referred to simply as NAND memories), with the size reduction, a bit error occurring at the time of reading has increased. For this reason, techniques for reducing errors in the entire system are important. Generally, in non-volatile semiconductor memories, data “1” is associated with an erase state, and data “0” is associated with a write state, but as the number of reciprocations of the write state and the erase state (hereinafter, referred to as the number of W/Es) increases while writing/erasing is being repeated, the number of electrons passing through an oxide film of a memory cell increases, leading to a state in which the memory cell is exhausted. Further, as writing is performed with a higher threshold voltage distribution, an interference effect on an adjacent memory cell increases, and a probability of bit errors being induced increases accordingly.